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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ERRPIDR1, Peripheral Identification Register 1</h1><p>The ERRPIDR1 characteristics are:</p><h2>Purpose</h2>
        <p>Provides discovery information about the component.</p>

      
        <p>For more information, see <span class="xref">'About the Peripheral identification scheme'</span>.</p>
      <h2>Configuration</h2><p>Implementation of this register is <span class="arm-defined-word">OPTIONAL</span>.</p>
        <p>ERRPIDR1 is implemented only as part of a memory-mapped group of error records.</p>
      <h2>Attributes</h2>
        <p>ERRPIDR1 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="24"><a href="#fieldset_0-31_8">RES0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">DES_0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">PART_1</a></td></tr></tbody></table><h4 id="fieldset_0-31_8">Bits [31:8]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-7_4">DES_0, bits [7:4]</h4><div class="field">
      <p>Designer, JEP106 identification code, bits [3:0]. ERRPIDR1.DES_0 and <a href="ext-errpidr2.html">ERRPIDR2</a>.DES_1 together form the JEDEC-assigned JEP106 identification code for the designer of the component. The parity bit in the JEP106 identification code is not included. The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.</p>
    
      <div class="note"><span class="note-header">Note</span>
        <p>For a component designed by Arm Limited, the JEP106 identification code is <span class="hexnumber">0x3B</span>.</p>
      </div>
      <p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-3_0">PART_1, bits [3:0]</h4><div class="field"><p>Part number, bits [11:8].</p>
<p>The part number is selected by the designer of the component. The designer chooses whether to use a 12-bit or a 16-bit part number:</p>
<ul>
<li>If a 12-bit part number is used, then it is stored in ERRPIDR1.PART_1 and <a href="ext-errpidr0.html">ERRPIDR0</a>.PART_0. There are 8 bits, <a href="ext-errpidr2.html">ERRPIDR2</a>.REVISION and <a href="ext-errpidr3.html">ERRPIDR3</a>.REVAND, available to define the revision of the component.
</li><li>If a 16-bit part number is used, then it is stored in <a href="ext-errpidr2.html">ERRPIDR2</a>.PART_2, ERRPIDR1.PART_1 and <a href="ext-errpidr0.html">ERRPIDR0</a>.PART_0. There are 4 bits, <a href="ext-errpidr3.html">ERRPIDR3</a>.REVISION, available to define the revision of the component.
</li></ul>
      <p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h2>Accessing ERRPIDR1</h2><h4>ERRPIDR1 can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>RAS</td><td><span class="hexnumber">0xFE4</span></td><td>ERRPIDR1</td></tr></table><p>Accesses on this interface are <span class="access_level">RO</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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